Memory reliability problems are a result of decreasing device structure sizes along with increasing numbers of transistors due to increasing memory size. Memories have been protected against hard fails using Error Correction Code (ECC) Single Error Correction Double Error Detection (SECDED) encoding. ECC SECDED is not an ideal approach for some applications due to its drawback of requiring more transistors and hence a massive overhead in terms of area and power. This is especially a problem for systems where it is necessary to conduct small write accesses that can not be mapped into read-modify-write accesses due to performance restrictions.
As illustrated in Table 1 below, in ECC SECDED encoding the number of ECC bits is logarithmically proportional to the number of data bits, and thus smaller access widths cause more overall overhead than wide access widths. If the write access width is only 16 bits, then there are 6 extra ECC bits per 16 data bits. These narrow writes could not be mapped into wider read-modify-write accesses due to performance restrictions.
TABLE 1Ratio of Error Correcting Code vs. “Normal” Information Using SECDEDWidth of Width of requiredRatio of errornormal data SECDED code correcting code/nword 2n(n + 2)normal information38562.50%416637.50%532721.88%664812.50%71289 7.03%